Researchers, companies and institutions are interested in understanding errors in a circuit. One such example is an error introduced by on-chip variations (e.g. by process/voltage/temperature variations). Particularly, these entities are interested to find out when an error may occur and how to prevent it. This will allow these entities to detect possible errors in a circuit and prepare how to prevent such errors.
As such, resources are invested to identify and predict an error in a circuit. In order to do so, great effort has been taken to identify an error in a circuit, especially so in recent times, as advanced technology nodes are adopted to improve performance and reduce power consumption which results in increasing on-chip variability. Consequently, this causes error in circuits. It is important to design the circuits such that delay and power consumption are minimised or prevented, without compromising the reliability of circuits.
Conventional means of determining an error in a circuit include using global variation detection techniques (e.g. on-chip variation sensor and critical path replica) for sensing the error and tuning the clock or supply voltage accordingly. One of the problems of such conventional means is that they tend to provide an analysis without capturing the local variations of the circuit such as the within-die variation and power supply noise.
In order to overcome the shortcomings of adaptive tuning circuits, in-situ variation detection techniques are used to capture the local variations. There are mainly two types of in-situ error detection techniques, namely Razor and Canary. According to the Razor technique, a shadow flip flop is used to detect timing errors at a destination flip flop. However, one disadvantage of this technique is that the error detection is performed after the clock rising edge of the clocking signal. Therefore, in order to differentiate late-arriving data from early-arriving data, the minimum path delay has to be adjusted to be longer than the detection period by inserting buffers. This effectively increases the hold time constraint of the flip flop, and causes significant overhead in area and power consumption. It can also cause problems for timing closure because fixing the hold time for one path can easily violate the setup time for another path, especially for low voltage operation where the fluctuation of delays in path is significant. Another disadvantage of this technique is that the correction is performed through architectural replay, which is only available in high-performance processors supporting branch prediction. As such, this prevents the application of this technique to a general design.
Another conventional in-situ variation detection technique that is commonly used is the Canary technique. According to the Canary technique, a flip flop is used to predict the error by capturing the artificially delayed data at the receiver flip flop. This is done in combination with dynamic voltage scaling in a way that the supply voltage will be step-by-step decreased from nominal voltage until an error is predicted to find out the lowest operating voltage (for lowest power consumption) with correct functionality.
The advantage of this technique is that it does not require inserting buffer time which means less overhead and easier for timing closure. However, in practice, some critical paths may not be activated during a monitoring time period (before decreasing voltage at each step) which means that errors will still occur in the circuit without any prediction. A way to reduce the risk is to make the monitoring time period sufficiently long before decreasing voltage so as to activate most of the critical paths. However, this will reduce the energy efficiency achieved, and it still cannot eliminate the error because the path may be activated at an unpredictable time. Additionally, this technique does not prevent errors caused by fast dynamic variation such as power supply noise and soft error since they are unpredictable. As such, these techniques are typically suitable for applications where errors are allowable, for example, image or video codec.
Thus, what is needed is a method and circuit for detecting and correcting error in digital circuits that is easy to apply to a general design, without a lot of overhead. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.